2-input gates demo

And the code
library ieee;
use ieee.std_logic_1164.all;

entity Gates2 is
port (
btnL, btnR : in std_logic;
ledL, ledR : out std_logic;
led : out std_logic_vector (5 downto 0));
end entity;

-- 2-input gates demo
architecture meh of Gates2 is
signal L,R : std_logic;
L <= not btnL; R <= not btnR; -- copy inputs to LEDs ledL <= L; ledR <= R; -- gates led(0) <= L and R; led(1) <= L nand R; led(2) <= L or R; led(3) <= L nor R; led(4) <= L xor R; led(5) <= L xnor R; end architecture;