Vote counting


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity vote3 is
Port ( v : in STD_LOGIC_VECTOR (2 downto 0);
cnt : out STD_LOGIC_VECTOR (1 downto 0)
);
end vote3;

architecture meh of vote3 is
begin
cnt(1) <= (v(2) and v(1)) or (v(1) and v(0)) or (v(2) and v(0)); cnt(0) <= v(2) xor v(1) xor v(0); end meh;