library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

```
```entity g4fet is

Port ( x : in STD_LOGIC_VECTOR (2 downto 0);

z : out STD_LOGIC);

end g4fet;

`architecture meh of g4fet is`

begin

z <= (not x(2) and (x(1) nand x(0))) or (x(2) and (x(1) nor x(0)));
end meh;