4-1 multiplexer


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux41 is
port ( c : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
z : out STD_LOGIC);
end mux41;

architecture meh of mux41 is
signal w01, w23 : STD_LOGIC;
begin
w01 <= (not s(0) and c(0)) or (s(0) and c(1)); w23 <= (not s(0) and c(2)) or (s(0) and c(3)); z <= (not s(1) and w01) or (s(1) and w23); end meh;