4-1 multiplexer (using ‘case’ statement)


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux41c is
Port ( c : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
z : out STD_LOGIC);
end mux41c;

architecture meh of mux41c is
begin
p: process (c,s)
begin
case s is
when "00" => z <= c(0); when "01" => z <= c(1); when "10" => z <= c(2); when "11" => z <= c(3); when others => z <= c(0); end case; end process; end meh;