top level (test code)


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity top is
Port ( mclk : in STD_LOGIC;
sw : in STD_LOGIC_VECTOR (7 downto 0);
btn : in STD_LOGIC_VECTOR (4 downto 0);
ld : out STD_LOGIC_VECTOR (7 downto 0));
end top;

architecture meh of top is
component vote3 is
port ( v : in STD_LOGIC_VECTOR (2 downto 0);
cnt : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;

component g4fet is
port ( x : in STD_LOGIC_VECTOR (2 downto 0);
z : out STD_LOGIC
);
end component;

component mux21 is
port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : in STD_LOGIC;
z : out STD_LOGIC
);
end component;

component mux41 is
port ( c : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
z : out STD_LOGIC
);
end component;

component qmux21 is
port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC;
z : out STD_LOGIC_VECTOR (3 downto 0));
end component;

begin
ld(7 downto 4) <= sw(7 downto 4); qm: qmux21 port map ( a => sw(7 downto 4),
b => sw(4 downto 1),
s => sw(0),
z => ld(3 downto 0)
);

-- ld(7 downto 4) <= mclk & mclk & mclk & mclk; -- mux: mux21 -- port map ( -- a => sw(7),
-- b => sw(6),
-- s => sw(5),
-- z => ld(0)
-- );

-- mux: mux41
-- port map (
-- c => sw(7 downto 4),
-- s => sw(3 downto 2),
-- z => ld(0)
-- );

-- voting: vote3
-- port map (
-- v => sw(2 downto 0),
-- cnt => ld(1 downto 0)
-- );

-- fet: g4fet
-- port map (
-- x => sw(5 downto 3),
-- z => ld(3)
-- );

end meh;