display 4-digit number

signal clkdiv: std_logic_vector(20 downto 0);
signal x: std_logic_vector(15 downto 0);
signal digit: std_logic_vector(3 downto 0);
signal s: std_logic_vector(1 downto 0);

begin
ld <= sw; x <= X"ABCD"; s <= clkdiv(20 downto 19); seg7: hex7seg port map( x => digit,
a_to_g => a_to_g
);

-- clock divider
process (mclk)
begin
if rising_edge(mclk) then
clkdiv <= clkdiv + 1; end if; end process; -- select enable display position process (s) begin case s is when "00" => an <= "1110"; when "01" => an <= "1101"; when "10" => an <= "1011"; when others => an <= "0111"; end case; end process; -- select digit to display process (s,x) begin case s is when "00" => digit <= x(3 downto 0); when "01" => digit <= x(7 downto 4); when "10" => digit <= x(11 downto 8); when others => digit <= x(15 downto 12); end case; end process; end meh;