`library IEEE;`

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

```
```entity accum is

port ( a : in std_logic_vector (3 downto 0);

b : in std_logic_vector (3 downto 0);

clk : in std_logic;

accum_out : out std_logic_vector (7 downto 0));

end accum;

`architecture meh of accum is`

signal a_reg : std_logic_vector (3 downto 0);

signal b_reg : std_logic_vector (3 downto 0);

signal mult_reg : std_logic_vector(7 downto 0);

signal adder_out : std_logic_vector(7 downto 0);

begin

mult_reg <= a_reg * b_reg;
process(clk)
begin
if (rising_edge(clk)) then
a_reg <= a;
b_reg <= b;
adder_out <= adder_out + mult_reg;
end if;
end process;
accum_out <= adder_out;
end meh;