debounce


l: debounce
port map (
inp => lbtn,
clk => clkdiv(16),
outp => left_r
);

entity debounce is
port (
inp : in std_logic;
clk : in std_logic;
outp : out std_logic
);
end entity;

architecture meh of debounce is
signal s1,s2,s3 : std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
s1 <= inp; s2 <= s1; s3 <= s2; end if; end process; outp <= s1 and s2 and s3; end architecture;