display 4-digit number

signal clkdiv: std_logic_vector(20 downto 0);
signal x: std_logic_vector(15 downto 0);
signal digit: std_logic_vector(3 downto 0);
signal s: std_logic_vector(1 downto 0);

begin
ld <= sw; x <= X"ABCD"; s <= clkdiv(20 downto 19); seg7: hex7seg port map( x => digit,
a_to_g => a_to_g
);

-- clock divider
process (mclk)
begin
if rising_edge(mclk) then
clkdiv <= clkdiv + 1; end if; end process; -- select enable display position process (s) begin case s is when "00" => an <= "1110"; when "01" => an <= "1101"; when "10" => an <= "1011"; when others => an <= "0111"; end case; end process; -- select digit to display process (s,x) begin case s is when "00" => digit <= x(3 downto 0); when "01" => digit <= x(7 downto 4); when "10" => digit <= x(11 downto 8); when others => digit <= x(15 downto 12); end case; end process; end meh;

qmux 4-1


entity qmux41 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
c : in STD_LOGIC_VECTOR (3 downto 0);
d : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
z : out STD_LOGIC_VECTOR (3 downto 0));
end qmux41;

architecture meh of qmux41 is

begin
process (s)
begin
case s is
when "00" => z <= a; when "01" => z <= b; when "10" => z <= c; when other => z <= d; end case; end process; end meh;

7-segment decoder


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity hex7seg is
port ( x : in STD_LOGIC_VECTOR (3 downto 0);
a_to_g : out STD_LOGIC_VECTOR (6 downto 0));
end hex7seg;

architecture meh of hex7seg is

begin
process(x)
begin
case x is
when "0000" => a_to_g <= "0000001"; -- 0 when "0001" => a_to_g <= "1001111"; -- 1 when "0010" => a_to_g <= "0010010"; -- 2 when "0011" => a_to_g <= "0000110"; -- 3 when "0100" => a_to_g <= "1001100"; -- 4 when "0101" => a_to_g <= "0100100"; -- 5 when "0110" => a_to_g <= "0100000"; -- 6 when "0111" => a_to_g <= "0001111"; -- 7 when "1000" => a_to_g <= "0000000"; -- 8 when "1001" => a_to_g <= "0000100"; -- 9 when "1010" => a_to_g <= "0001000"; -- A when "1011" => a_to_g <= "1100000"; -- B when "1100" => a_to_g <= "0110001"; -- C when "1101" => a_to_g <= "1000010"; -- D when "1110" => a_to_g <= "0110000"; -- E when others => a_to_g <= "0111000"; -- F end case; end process; end meh;

top level (test code)


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity top is
Port ( mclk : in STD_LOGIC;
sw : in STD_LOGIC_VECTOR (7 downto 0);
btn : in STD_LOGIC_VECTOR (4 downto 0);
ld : out STD_LOGIC_VECTOR (7 downto 0));
end top;

architecture meh of top is
component vote3 is
port ( v : in STD_LOGIC_VECTOR (2 downto 0);
cnt : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;

component g4fet is
port ( x : in STD_LOGIC_VECTOR (2 downto 0);
z : out STD_LOGIC
);
end component;

component mux21 is
port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : in STD_LOGIC;
z : out STD_LOGIC
);
end component;

component mux41 is
port ( c : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
z : out STD_LOGIC
);
end component;

component qmux21 is
port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC;
z : out STD_LOGIC_VECTOR (3 downto 0));
end component;

begin
ld(7 downto 4) <= sw(7 downto 4); qm: qmux21 port map ( a => sw(7 downto 4),
b => sw(4 downto 1),
s => sw(0),
z => ld(3 downto 0)
);

-- ld(7 downto 4) <= mclk & mclk & mclk & mclk; -- mux: mux21 -- port map ( -- a => sw(7),
-- b => sw(6),
-- s => sw(5),
-- z => ld(0)
-- );

-- mux: mux41
-- port map (
-- c => sw(7 downto 4),
-- s => sw(3 downto 2),
-- z => ld(0)
-- );

-- voting: vote3
-- port map (
-- v => sw(2 downto 0),
-- cnt => ld(1 downto 0)
-- );

-- fet: g4fet
-- port map (
-- x => sw(5 downto 3),
-- z => ld(3)
-- );

end meh;

4-1 multiplexer (using ‘case’ statement)


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux41c is
Port ( c : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
z : out STD_LOGIC);
end mux41c;

architecture meh of mux41c is
begin
p: process (c,s)
begin
case s is
when "00" => z <= c(0); when "01" => z <= c(1); when "10" => z <= c(2); when "11" => z <= c(3); when others => z <= c(0); end case; end process; end meh;

4-1 multiplexer


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux41 is
port ( c : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
z : out STD_LOGIC);
end mux41;

architecture meh of mux41 is
signal w01, w23 : STD_LOGIC;
begin
w01 <= (not s(0) and c(0)) or (s(0) and c(1)); w23 <= (not s(0) and c(2)) or (s(0) and c(3)); z <= (not s(1) and w01) or (s(1) and w23); end meh;

2-1 multiplexer


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux21 is
port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : in STD_LOGIC;
z : out STD_LOGIC);
end mux21;

architecture meh of mux21 is
begin
z <= (not s and a) or (s and b); end meh;

4-input universal gate


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity g4fet is
Port ( x : in STD_LOGIC_VECTOR (2 downto 0);
z : out STD_LOGIC);
end g4fet;

architecture meh of g4fet is
begin
z <= (not x(2) and (x(1) nand x(0))) or (x(2) and (x(1) nor x(0))); end meh;

Vote counting


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity vote3 is
Port ( v : in STD_LOGIC_VECTOR (2 downto 0);
cnt : out STD_LOGIC_VECTOR (1 downto 0)
);
end vote3;

architecture meh of vote3 is
begin
cnt(1) <= (v(2) and v(1)) or (v(1) and v(0)) or (v(2) and v(0)); cnt(0) <= v(2) xor v(1) xor v(0); end meh;

2-input gates demo

And the code
library ieee;
use ieee.std_logic_1164.all;

entity Gates2 is
port (
btnL, btnR : in std_logic;
ledL, ledR : out std_logic;
led : out std_logic_vector (5 downto 0));
end entity;

-- 2-input gates demo
architecture meh of Gates2 is
signal L,R : std_logic;
begin
L <= not btnL; R <= not btnR; -- copy inputs to LEDs ledL <= L; ledR <= R; -- gates led(0) <= L and R; led(1) <= L nand R; led(2) <= L or R; led(3) <= L nor R; led(4) <= L xor R; led(5) <= L xnor R; end architecture;